📘 Chandigarh University – MCA/BCA/B.Tech
These Mid-Semester papers are part of the official examinations of Chandigarh University,
designed to test knowledge and practical understanding of core MCA, Computer Applications, and B.Tech subjects.
💡 Each paper encourages students to think critically, apply concepts, and showcase problem-solving skills — helping them prepare for real-world IT challenges.
Usage Condition:
- 📖 Papers are for reference and study purposes only.
- 🧑🎓 Students should use them responsibly and not for any malpractice.
- 📅 Availability depends on the course and year.
-
Instructions:
-
The question paper is consisting of three sections.
-
It is compulsory for students to attempt all questions of Section A and Section B.
-
Question no. 10 & 11 of Section C are compulsory to be attempted.
-
Students to attempt any one question from question no. 12 & question no. 13 of Section C.
-
Computer Organization and Architecture
Subject Code: 24CST-201 / 24IT-201
Semester: 3 | Time: 3 Hours | Max Marks: 60
Section -A
| Q. No | Statement | CO Mapping | BT Level |
|---|---|---|---|
| 1 | Explain the role of system buses in a digital computer. | CO1 | 1 |
| 2 | What is the difference between RISC and CISC architecture? | CO2 | 2 |
| 3 | What is DMA in I/O data transfer? | CO4 | 1 |
| 4 | Define speedup. A non-pipelined processor takes 60 ns per instruction. A pipelined design takes 15 ns. Compute the speedup. | CO4 | 2 |
| 5 | a) In what ways does an I/O Processor reduce CPU burden during data transfer? | ||
| b) If the CPU is busy 80% of the time handling I/O operations and with an IOP (I/O processor) this reduces to 20%, find the CPU utilization. | CO4 | 2 |
Section B (4 × 5 = 20 marks)
| Q. No | Statement | CO Mapping | BT Level |
|---|---|---|---|
| 6 | Using 4-bit 2’s complement representation, apply Booth’s multiplication algorithm to compute the product of (-5) × (+3). Illustrate all intermediate steps including initialization, arithmetic operations and bit-shifting. Conclude with the final binary and decimal result. | CO1 | 3 |
| 7 | “Simulate the FIFO page replacement algorithm for the page reference string: 1, 2, 5, 1, 2, 5, 1, 2, 3, 4, 5. Analyze the results under the following conditions: | ||
| a) Calculate the number of page faults using 3 frames and 4 frames. | |||
| b) Evaluate whether Belady’s anomaly is observed, and explain its significance.” | CO3 | 4 | |
| 8 | Describe interrupt-driven data transfer. How does it differ from programmed I/O? | CO4 | 3 |
| 9 | Explain different pipeline hazards. How do they affect system performance? | CO3 | 3 |
Section C (3 × 10 = 30 marks)
| Q. No | Statement | CO Mapping | BT Level |
|---|---|---|---|
| 10 | Discuss the different instruction formats in computer architecture. Explain the role of addressing modes with examples. | CO4 | 3 |
| 11 | Explain hardwired and microprogrammed control units. Compare them on the basis of speed, cost, and flexibility. | CO5 | 3 |
Optional Question of Section C
| Q. No | Statement | CO Mapping | BT Level |
|---|---|---|---|
| 12 | Evaluate the impact of instruction-level parallelism and pipeline depth on system throughput. Illustrate with numerical examples. | CO5 | 3 |
| OR | |||
| 13 | Critically analyze different pipeline performance enhancement techniques. How do branch prediction and hazard mitigation improve execution efficiency? | CO5 | 4 |
